Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits

In this paper, we deal with the case that aggressor is a data line and victim is a clock line. And we assume that aggressor and victim corresponds to one-to-one. In addition, we handle the circuit that a clock buffer is inserted in the clock line of every FF. Hence, only one FF is affected by an additional clock as shown hatched FF in Fig. 1. In the proposed BIST circuit, switches are inserted in inputs of state FFs as shown in Fig. 1. In the test mode, switches are opened to disconnect inputs of FFs and outputs of the combinational circuit. And LFSRs with the pre-determined number of stages are configured by using state FFs. These LFSRs have the same characteristic polynomial. If the total number of FFs in the circuit is not a multiple of LFSR stages, a proper number of FFs are added to the circuit. Primary inputs are connected to LFSRs to apply test vectors as shown in Fig. 1. Likewise the state FF, these LFSRs are configured with the pre-determined number of stages and have the same characteristic polynomial. But the characteristic polynomial of LFSRs connected to primary inputs is different from the characteristic polynomial of state FFs. Moreover, we configure the LFSRs by using the input block FFs of this chip in order to implement the BIST circuit with low area overhead. Delay gates are inserted in outputs of LFSRs as shown in Fig. 1. In the test mode, outputs of LFSRs are connected through delay gates in order to avoid a setup violation. In the normal mode, delay gates are bypassed through the bypass line attached to delay gates shown as a dotted line in Fig. 1. When a crosstalk pulse is generated on a clock line as an additional clock pulse, the FF changes its value if the input and the output of the FF have different values. Therefore the LFSR including the affected FF has different value with other LFSRs. As shown in Fig. 1, the bottom position of LFSR is connected to the comparator. The fault can be detected by comparing the value of this position for every clock.